Field
Aspects of the disclosure relate generally to electronic circuits, and more specifically, but not exclusively, to a reconfigurable three-dimensional (3D) integrated circuit (IC).
Background
Conventional three-dimensional integrated circuit (3D-IC) architectures include a so-called 2.5D architecture and a fully stacked three-dimensional (3D) architecture. In a 2.5D architecture, dies are placed side-by-side and interconnected via a horizontal interposer layer. A fully stacked 3D architecture employs dies that are stacked on top of one another. Both architectures use through-silicon vias (TSVs) to connect the metal layers.
Existing 3D-IC routing design faces several critical challenges relating to power distribution network (PDN) design and thermal management. A typical 3D-IC PDN is implemented as a pyramid shape where power rails are used to supply the power from the bottom of the IC to the top of the IC. This PDN occupies significant die area and leads to routing congestion. Regarding thermal management, when multiple dies are stacked together, it is difficult to dissipate the heat, especially for bottom dies. This can lead to a dramatic degradation in overall system performance at high temperatures. Accordingly, there is a need for a new architecture that resolves PDN design and thermal management issues associated with 3D-IC.